Director, Memory Design at Kepler Computing

Kepler is building a new class of AI memory and logic.

We combine advanced materials, 3D architectures and deep semiconductor expertise to address fundamental physical limits in computing, including the space and energy required to support growing compute demands.

Our team has shipped technologies used in billions of devices and by hundreds of millions of people. We are backed by pioneers in computing and leading semiconductor companies and work alongside major customers and partners to move new technology from the lab toward real-world application.

At Kepler, you’ll work with curious, driven people solving complex technical challenges through experimentation, evidence and iteration. Your work will contribute directly to the technologies we’re building and to the computing capacity they can make possible.

About the Role:

We are looking for a highly experienced and technically deep Director, Memory Design to own and drive the design of a custom memory controller for Kepler's next-generation UHBM-based 3D-memory AI accelerator platform. This is a highly specialized, high-impact technical role sitting at the critical intersection of custom DRAM architecture, digital logic design, and SoC integration. The ideal candidate will bring deep hands-on expertise in memory controller architecture and RTL design, with a strong understanding of 3D DRAM connectivity via distributed TSV fabrics, low-latency access path design, and state-of-the-art memory subsystem optimization for AI inference workloads. This role demands someone who can both architect and implement; taking an existing memory controller design and significantly modifying or extending it to meet the unique requirements of Kepler's custom 3D DRAM architecture, making well-reasoned VLSI trade-off decisions throughout.

Responsibilities:

Memory Controller Architecture & Design Ownership

• Own and drive the end-to-end design of the custom memory controller for Kepler's UHBM-based 3D DRAM from architecture definition and micro-architecture specification through RTL implementation, verification integration and tapeout signoff.

• Architect and implement a low-latency, state-of-the-art memory access path optimized for the unique topology of Kepler's distributed TSV-based connectivity to DRAM banks and channels stacked above/below the base die.

• Create or significantly modify an existing memory controller design to meet product-specific requirements - including custom DRAM command/address protocols, timing parameters, refresh strategies, bank and channel interleaving and power management.

• Define and optimize the distributed TSV interface architecture - including TSV PHY interaction, signal integrity constraints, timing budgeting across the die-to-DRAM interface and error detection/correction (ECC) strategy.

• Develop micro-architecture specifications for all key memory controller sub-blocks - including scheduler, command/address path, data path, ECC engine, refresh controller, power-down/self-refresh management and training/initialization state machines.

• Drive PPA optimization across the memory controller - making well-reasoned trade-offs between access latency, bandwidth efficiency, area and power in the context of AI inference workload access patterns.

Design Implementation & Quality

• Implement high-quality, lint-clean, CDC-clean RTL for the memory controller and associated subsystems in SystemVerilog; ensure RTL is synthesis-ready and meets design coding guidelines.

• Own implementation convergence — drive LINT, CDC/RDC, LEC, synthesis, SDC constraint development, timing closure interaction and bug fix resolution through to tapeout.

• Develop and validate SDC timing constraints for the memory controller - including TSV interface timing, internal datapath constraints and multi-cycle/false path exceptions.

• Drive and support physical design interaction - provide floorplan guidance, pin placement inputs, power domain definitions and timing budget inputs to the physical design team for memory controller implementation.

• Perform and review functional and formal verification of the memory controller - work closely with the verification team to define the verification plan, develop directed tests and achieve coverage closure.

• Ensure regular design reviews, quality checks, and sign-offs against schedule milestones.

3D DRAM & TSV Interface Expertise

• Define and implement the distributed TSV connectivity architecture - work with architecture and packaging teams to define TSV assignment, channel mapping and signal integrity requirements for the DRAM-to-base-die interface.

• Develop DRAM timing models and interface specifications - define tRCD, tCL, tRP, tRAS, tREFI, and other custom DRAM timing parameters relevant to the 3D DRAM technology; ensure the controller correctly implements all required timing margins.

• Implement and validate DRAM training and initialization sequences - including write/read leveling, gate training, DQ/DQS alignment and ZQ calibration adapted for the custom 3D DRAM interface.

• Define and drive ECC architecture - select and implement appropriate ECC scheme (SEC-DED, ChipKill, or custom) suitable for the 3D DRAM's reliability requirements and latency budget.

Cross-Functional Collaboration

• Work closely with SoC architecture and Chip Lead teams to ensure the memory controller micro-architecture aligns with overall SoC memory subsystem requirements, AI dataflow access patterns and bandwidth/latency KPI targets.

• Collaborate with physical design, packaging, and foundry teams to ensure memory controller implementation is feasible from a backend, TSV placement, power delivery and signal integrity perspective.

• Interface with the verification and emulation teams - support memory controller model integration into the SoC verification environment and FPGA/emulation platform for pre-silicon software bring-up.

• Engage with 3D DRAM technology partners and IP vendors - define interface requirements, review DRAM specifications and ensure controller-to-DRAM compatibility and compliance.

• Work with post-silicon validation teams - define bring-up sequences, diagnostic test strategies, and characterization plans for the memory controller and TSV interface.

Methodology & Documentation

• Establish memory controller design and integration best practices - RTL coding standards, interface protocol documentation, timing constraint guidelines and review processes.

• Document and maintain memory controller micro-architecture specifications, interface specs, training sequence documentation and tapeout signoff checklists.

• Mentor junior engineers on memory subsystem design; contribute to team knowledge sharing on 3D DRAM design challenges and methodologies.

Requirements:

• B.Tech / M.Tech / MS / PhD in Electrical Engineering, Electronics & Communication, Computer Engineering or related discipline.

• 15–20 years of hands-on experience in memory controller architecture and RTL design with multiple successful SoC tapeouts involving complex memory subsystems.

• Deep expertise in DRAM memory controller design; scheduler architecture, command/address path, datapath, ECC, refresh management, power-down and training/initialization state machines.

• Strong hands-on experience creating or significantly modifying memory controller RTL to meet custom product requirements not just integration of existing IP.

• Deep understanding of DRAM timing parameters and protocol; DDR4/DDR5, LPDDR4/LPDDR5, HBM2/HBM3 or custom DRAM protocols; ability to adapt controller behavior to non-standard or custom DRAM specifications.

• Solid understanding of 3D memory integration challenges; TSV-based connectivity, die stacking, signal integrity across TSV channels and associated timing/power implications.

• Hands-on experience with SoC front-end implementation flows; LINT, CDC/RDC, LEC, synthesis (Genus / Design Compiler), SDC constraint development and formal verification.

• Strong grasp of VLSI design trade-offs; latency vs. bandwidth, area vs. power, scheduling policy vs. QoS and ability to make and justify design decisions in the context of AI accelerator workloads.

• Solid understanding of physical design interaction; timing closure, floorplanning inputs, power integrity and TSV placement constraints.

• Proficiency in SystemVerilog RTL design; clean, lint-free, CDC-safe, synthesis-ready code.

• Experience with ECC architecture and implementation;SEC-DED, ChipKill, or custom ECC schemes for memory reliability.

• Strong scripting skills; Python, Perl, Tcl for flow automation, timing analysis, and memory subsystem characterization.

• Self-driven with strong ability to work across teams; demonstrated ability to own and deliver complex design blocks end-to-end.

Nice to Have:

• Hands-on experience with HBM (HBM2/HBM2E/HBM3) base die design or custom logic base die; including base die memory controller implementation, PHY interaction, and TSV interface design; this is a strong differentiator for this role.

• Experience with custom or proprietary DRAM interface design; beyond standard JEDEC protocols; ability to work from a DRAM vendor specification and implement a compliant, optimized controller.

• Understanding of AI/ML memory access patterns; specifically inference workload characteristics, activation memory access, weight streaming and KV-cache bandwidth requirements.

• Experience with memory controller performance modeling - bandwidth and latency simulation, queue depth analysis and scheduling policy evaluation using analytical or cycle-accurate models.

• Knowledge of CXL memory protocols and their implications for memory controller architecture in multi-chip AI accelerator platforms.

• Exposure to DRAM PHY design interaction - DQ/DQS training, impedance calibration and PHY-controller interface timing.

• Familiarity with chiplet and 2.5D/3D-IC integration challenges - interposer design, multi-die power delivery and cross-die timing constraints.

• Experience with post-silicon memory subsystem bring-up and characterization - DRAM training debug, margin testing and bandwidth/latency characterization.

• Prior startup experience - demonstrated ability to deliver high-quality, custom silicon with lean teams and aggressive timelines.

Compensation and Benefits

Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, job responsibilities and work location.

Kepler offers a comprehensive benefits package to eligible employees, including medical, dental and vision coverage, retirement benefits, paid time off and additional Kepler benefits as applicable. Eligibility and benefit offerings may vary based on employment status and work location.

Equal Employment Opportunity

Kepler is an Equal Opportunity Employer. We provide equal employment opportunities to all applicants and employees and do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law.

We believe that different backgrounds, experiences, perspectives and ideas make our team stronger and help our employees, our technology and our community thrive.

Reasonable Accommodation

Kepler is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you need a reasonable accommodation to participate in the application or interview process, please contact us at 408-365-4627 or [email protected].

Fair Chance Hiring

Kepler will consider qualified applicants with criminal histories in accordance with applicable federal, state, and local laws, including the California Fair Chance Act. Applicants are not required to disclose criminal history before a conditional offer of employment except where otherwise permitted or required by applicable law.

Federal Contractor Notice

Kepler is a federal contractor or subcontractor and is committed to its obligations regarding equal employment opportunity. Kepler does not discriminate against qualified individuals on the basis of disability or protected veteran status and takes steps to employ and advance in employment qualified individuals with disabilities and protected veterans.