Senior Digital Verification Engineer at Efficient Computer
Efficient Computer is hiring a Senior Digital Verification Engineer in Austin, TX, US +2 more. On-site. Pay: USD 160k-245k/yr.
About Efficient Computer
Efficient Computer designs energy-efficient general-purpose AI chips for edge devices and embedded systems. Its Fabric architecture uses a spatial dataflow approach to distribute workloads, and its Electron E1 processor aims to achieve accelerator-class efficiency while remaining programmable. The company claims up to 100 times better energy efficiency than low-power CPUs, targeting applications such as edge AI, on-device inference, IoT devices, and industrial automation.
Senior Digital Verification Engineer job description
Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution
We are looking for an experienced Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team. This is a great opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!
Required Qualifications & Experience
- Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience: 10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout.
- UVM and SystemVerilog: Expertise in UVM-based testbench architecture and constrained-random verification methodology
- C/C++ experience for modelling or verification.
- Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
- Debug Skills: Proven ability to debug complex simulation failures.
- Scripting & Automation: Proficiency in Python for test automation, log analysis, coverage post-processing, and regression flow development.
- Communication: Ability to clearly communicate verification risk, status and tradeoffs to technical peers and program leadership.
Ways to stand out :
- Experience in Formal verification (JasperGold or similar).
- Experience building or using AI Agentic flows for DV.
- Software/Firmware based testing experience and working with software teams pre-silicon
- Post-silicon experience
- SoC Architecture: Understanding and experience in some of the following areas : processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
- Power aware verification and UPF
We offer a competitive base salary for this role, generally ranging from $160,000 to $245,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.
Why Join Efficient?
Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.
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